Performance

iPhone 12 to Have Major Performance Improvements

Apple’s upcoming iPhone 12 lineup is likely to see major performance and efficiency improvements thanks to the A14 Bionic Processor.

Our first glimpse at the A14 comes from the just announced iPad Air 4, which is the first device to sport the next-generation Apple-designed processor. The 64-bit desktop-class A14 Bionic chip sees a considerable leap in performance and efficiency, according to Apple.

Early benchmarks suggest that the A14 is a 6-core chip with a base frequency of 2.99GHz and 3.66GB of memory, achieving a score of 1,583 in single-core and 4,198 for multi-core.

This is markedly higher than the 1,336 in single-core and 3,569 in multi-core for the A13 Bionic from 2019’s iPhone 11 lineup. Roughly compared, that means the iPhone 12 will be 18.4% faster in single-core performance and 17.6% faster than the current top-of-the-line iPhone. Here are speed comparisons of the upcoming iPhone 12 processor with other recent iPhone models (single core performance):

  • iPhone 6s / SE – 196% Faster
  • iPhone 7 – 117% Faster
  • iPhone 8 – 75% Faster
  • iPhone XR / XS – 44% Faster
  • iPhone SE (2020) / 11 / 11 Pro – 18% Faster

Compared to the A12Z chip from the 2020 iPad Pro, the A14 does better than the A12Z in single-core at 1,118 and slightly lower than in multi-core at 4,564. The A12Z has an extra GPU core compared to the A12X, however. These early benchmarks indicate that the A14 offers noteworthy speed enhancements, even over the impressive A13 chip from last year.

Apple says the A14 Bionic chip has a “next-generation” 16-core Neural Engine that delivers 11 trillion operations per second, which is more than twice as many as the A12 chip. There are new-to-mobile accelerators that reportedly deliver up to 10 times better machine learning performance. There is also improved

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Silexica’s SLX FPGA 2020.3 Delivers 2x Performance Improvements for FinTech

SAN JOSE, Calif., Oct. 5, 2020 /PRNewswire/ — Silexica (silexica.com) has announced the release of SLX FPGA 2020.3 with 2x performance improvements for FinTech design sets compared to the previous release, SLX FPGA 2020.2. These enhancements empower financial institutions and exchanges to optimize their designs and decrease time-to-market. Further improvements to the area/performance models and the SLX FPGA optimization engine result in an overall performance increase of 1.24x across all designs, involving almost 100 benchmarks. The release of SLX FPGA 2020.3 further enables developers to convert C/C++ code into an FPGA more easily, faster, and with higher performance.

“In Fintech, next-generation compute acceleration is critical to solve fundamental challenges, such as improved latency and determinism,” said Jordon Inkeles, VP of Product at Silexica. “To enable these compute requirements, financial companies and exchanges are beginning to leverage programmable hardware and high-level synthesis (HLS) design methodology.”

SLX FPGA Enables Developers to Overcome HLS Challenges

Adopting an HLS methodology presents challenges that must be considered and overcome during the design process. SLX FPGA tackles the problems associated with the HLS design flow, including non-synthesizable C/C++ code, non-hardware aware C/C++ code, detecting application parallelism, and determining which pragmas to insert and the pragma attributes to help engineers prepare and optimize their C/C++ application code for HLS.

New features and enhancements to SLX FPGA 2020.3 include:

  • Significant improvements to the area/performance models and optimization engine.
  • The Xilinx® Support Archive (.xsa) file format supported by Xilinx® Vivado HLS 2019.2 can now be imported to SLX.
  • Support has been added for Xilinx® Vivado HLS 2020.1.
  • A number of usability enhancements have been introduced to make visualizations more clear and consistent.

As an active member of the Securities Technology Analysis Center (STAC), Silexica will be presenting at the Global STAC Summit™ on October 19th to discuss

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